1. Field of Use
The present invention relates to memory systems and more particularly to transfers of multiple words between a memory system and a data processing unit.
2. Prior Art
It is well known to construct a memory system from a plurality of memory modules. Certain prior art systems pair memory modules together to provide a double word fetch capability. The term double word fetch refers to the ability to access a pair of words at a time from a memory during a memory cycle of operation.
In such systems, it becomes desirable to be able to include the capability of transferring over a single bus during successive cycles of operation, groups of multiple words simultaneously accessed during a memory cycle of operation without incurring communication delays. This capability is termed a burst mode transfer. For an example of this type of system, reference may be made to U.S. Pat. Nos. 4,366,539 and 4,370,712.
In a high performance system, such as an Intel 486 based microprocessor and DRAM system, up to 16 bytes can be transferred at a time during a burst read operation. In such a system, the addresses of the data items in the burst read operation will all fall without the same 16-byte aligned area which corresponds to an internal microprocessor cache line. In each burst operation, it is required that the data words be returned to the requesting user in a special sequence which is a function of the first requested address received from the user. For example, if the first address was zero, the following addresses must be 4, 8 and C (Here). For an initial address of 4, the sequence is 0, C and 8. The remaining sequences are 8, C, 0, 4 and C, 8, 4 and 0.
It has been proposed that given the first address in a burst, external hardware can easily calculate the address of subsequent transfers in advance. This is discussed in the publication entitled, "i486.RTM. microprocessor", published by Intel Corporation, November, 1989. It has been found that capturing the first address in a register/counter implemented using a programmable array logic element (PAL) and then programming the PAL to generate the required address sequence earlier than required improves performance. However, this approach still requires that sufficient time be available in advance following receipt of the burst request to generate the particular address sequence. Also, there must be sufficient time provided to carry out the entire address generation process.
It is a primary object of the present invention to provide a system for generating a set of address sequences within a minimum amount of time.